As the dimensions in complementary metal oxide semiconductor (CMOS) devices are continually reduced, the drive current in such devices becomes limited by the parasitic series resistance of the ohmic contacts. The reduction in contact hole area drives the search for materials that can form an ohmic contact with very low resistivity.
One type of material commonly employed in fabricating ohmic contacts is metal silicides such as cobalt silicide. Cobalt silicide and other metal silicides are typically fabricated using a conventional self-aligned silicide (salicide) process, wherein a blanket TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over the exposed silicon regions (source, drain and gate) of transistors. A selective wet etch is employed to remove the TiN cap and the non-reacted cobalt left over the oxide or nitride regions. The cobalt monosilicide is then subjected to a second anneal which converts the monosilicide into a cobalt disilicide layer.
Although silicides of Ti, Co and Ni offer some of the properties needed to this point, an improvement in resistance of the ohmic contact is definitely needed for future generation of devices.
The Schottky barrier heights of a given material on n+ and p+ silicon substrates must add to 1.13 eV, the band gap of silicon. It is difficult however to find a material that lowers the contact resistance to both p-type and n-type material.
One obvious solution to the above problem is to use different materials for n- and p-type areas of a circuit. This, however, is not a financially suitable solution since it adds many additional processing steps to the overall fabrication scheme.
In view of the above-mentioned drawbacks with prior art processes, there is a continued need for developing a new and improved method of reducing contact resistance of metal silicides to at least the p+Si area of the substrate.